Never Cross a Ground Plane Gap in High Speed PCB Design
Make sure none of these traces crosses a ground plane gap
I often browse electronics and PCB forums, and I see the same question asked over and over: Why shouldn’t I route a trace over a split in my ground plane? This question gets asked by everyone from makers to professional designers who are just dipping their toes into high speed PCB design. For the professional signal integrity engineer, the answer should be obvious.
Whether you’re a long-time PCB layout engineer or a casual designer, it helps to understand the answer to this question. The answer is always framed as an always/never statement. I don’t often like to give answers in absolute terms to PCB design questions, but in this case the answer is clear: Never route a signal over a gap in a ground plane. Let’s dig into this further and get a sense for why you should not route a trace over a gap in a ground plane.
Ground Plane Gap: Low and High Speed Design
Answering this question requires considering how signals behave at DC, low speeds, and high speeds. This is because each type of signal will induce a different return path in this reference plane. The return path your signals follow will have some important effects on EMI that is generated within the board, as well as the susceptibility of a particular circuit to EMI. To get a better sense of how the return path forms in your PCB, take a look at this article, as well as this useful guide from Francesco Poderico.
If you understand how the return current forms in your PCB, then it becomes easy to see how it affects EMI and signal integrity. Here’s why it’s important—and it relates to routing over a ground plane gap. The loop formed by the return current in your board determines two important behaviors:
-
EMI susceptibility. The loop created by the supply and return current in a circuit determines the board’s susceptibility to EMI. A circuit with a large current loop will have larger parasitic inductance, making it more susceptible to radiated EMI.
-
Ringing in switching signals. The parasitic inductance in a circuit determines the level of damping experienced by the transient response in a circuit when a signal switches between levels. When taken alongside parasitic capacitance in your circuit, the two quantities determine the natural frequency of the transient response and the damped oscillation frequency.
Let’s look at DC, low speed, and high speed signals in detail:
DC Voltage/Current
When a board runs on DC power, the return current will not be produced directly below the signal trace; it will follow a straight line back to the supply return point. This means you essentially have no control over the return path, and the board can be susceptible to EMI due to the large parasitic inductance. One would think that, because the power supply is not switching, there would be no transient oscillation, thus it would not matter if a microstrip trace is routed over a ground plane gap. Although there is no oscillation, there is still the problem of the EMI susceptibility. You should try to keep the DC loop inductance as low as possible, and avoiding routing over a ground plane gap is the best idea to reduce loop inductance.
Low Speed Signals
Just like DC signals, the return path determines the loop inductance of the circuit, which determines EMI susceptibility and damping in the transient response. If the loop inductance is large, the damping rate will be lower and just as was the case with DC signals, routing over a ground plane gap increases the loop inductance, which affects signal integrity, power integrity, and EMI.
Unfortunately, low speed signals are something of a relic, and every board that uses TTL and faster logic will behave as a high speed circuit. With low speed signals (generally 10’s of ns rise times and slower), the ringing amplitude in a particular circuit was typically low enough that it went unnoticed. Therefore, as long as signals were not routed over a ground plane gap, the loop inductance was typically sufficiently low to prevent intense ringing, EMI susceptibility, and associated power integrity problems (see below).
High Speed Signals
If I take a board designed to run at low speed, and I run it with high speed signals, the ringing amplitude will be larger for a given circuit loop inductance. Again, this illustrates the need to keep the loop inductance in the board as small as possible. The goal is to provide as much damping as possible in order to reduce the ringing amplitude in a given interconnect. Again, routing over a ground plane gap will avoid increasing the loop inductance. In addition, a ground plane should be placed below the signal layer carrying high speed circuits in order to ensure the loop inductance is as low as possible throughout an interconnect.
Example return path for a signal routed over a ground plane gap.
Another way to view a ground plane gap is as an impedance discontinuity. If a signal is routed over a ground plane gap, the impedance of the region over the gap will be larger than the impedance of the remainder of the interconnect. This leads to signal reflection in addition to the exacerbated ringing problems mentioned above. Take a look at this article from Signal Integrity Journal to learn more about this aspect of high speed signalling over a ground plane gap.
Everything mentioned above regarding digital signals applies equally to analog signals. The transient signal problems mentioned above are related to power integrity problems, especially in boards that use high gate/pin count components. The layer stack should be specifically designed to support faster-than-TTL components (see below).
Power Rails and Ground Plane Gaps
Note that we’ve looked at this in terms of signal integrity, but the same ideas apply to power integrity. Just as microstrip traces should not be routed across a ground plane gap, you should also avoid routing power rails on the surface layer over a ground plane gap. If you are supplying DC power to a digital IC, the IC will draw some current from the power supply when it switches between the ON and OFF states. This will produce a voltage ripple on the power rail.
This particular transient response in the supply voltage behaves as a damped oscillation. Its amplitude is proportional to the impedance of the PDN and is inversely proportional to the level of damping in the PDN. Just like the damping is inversely proportional to the loop inductance in a standard PCB interconnect, the same applies to the transient response in a PDN. This means you can dampen the transient response on the power rail if you keep the loop inductance small. The best way to do this is to place the ground plane on a layer directly adjacent to the power plane and avoid routing any power rails over any ground plane gap.
If you are working with a two-layer board and you do not have room for ground planes, you should carefully plan return paths in your board so that you keep the loop inductance small. One option is to use a gridded arrangement of ground regions on the top and bottom layers and connect them with vias. However, if you are working with high speed signals (TTL and faster), you will see large voltage fluctuations on the power rails due to insufficient capacitance in the PDN. This is the primary reason that power and ground planes are placed on adjacent layers in high speed boards, and the ground plane is placed directly below the signal/component layer.
The powerful PCB design and analysis tools in Altium Designer® are built on top of a unified rules-driven design engine, allowing you to check the performance of your board as you create your layout. You’ll also have a complete set of tools for analyzing signal integrity and preparing deliverables for your manufacturer.
Now you can download a free trial of Altium Designer and learn more about the industry’s best layout, simulation, and production planning tools. Talk to an Altium expert today to learn more.
